Today I needed to learn about the RISC architecture to response one of my assignment in Advanced Computer Architecture module in the University. I studied about it in a rapid process. Because the deadline was very short. I had to submit that assignment within a ten minutes interval. But that is what normally happening. usually I do the assignments in the last minutes. But today assignment topic was new that is about RISC architecture. So after submitting that assignment I wish to post about that architecture for others references.
First of all what is RISC?
RISC is a 'Reduced Instruction Set Computer' which is a type of microprocessor architecture that utilizes a small, highly-optimized set of instructions, rather than a more specialized set of instructions often found in other types of architectures.
History about the RISC architecture
The first RISC projects came from IBM, Stanford, and UC-Berkeley in the late 70s and early 80s. The IBM 801, Stanford MIPS, and Berkeley RISC 1 and 2 were all designed with a similar philosophy which has become known as RISC. Certain design features have been characteristic of most RISC processors: 1 - one cycle execution time: RISC processors have a CPI (clock per instruction) of one cycle. This is due to the optimization of each instruction on the CPU and a technique called ; 2 - pipelining: a techique that allows for simultaneous execution of parts, or stages, of instructions to more efficiently process instructions; 3 - large number of registers: the RISC design philosophy generally incorporates a larger number of registers to prevent in large amounts of interactions with memory
RISC design philosophy In the mid 1970s researchers at IBM (and similar projects elsewhere) demonstrated that the majority of combinations of these orthogonal addressing modes and instructions were not used by most programs generated by compilers available at the time. It proved difficult in many cases to write a compiler with more than limited ability to take advantage of the features provided by conventional CPUs. It was also discovered that, on microcoded implementations of certain architectures, complex operations tended to be slower than a sequence of simpler operations doing the same thing. This was in part an effect of the fact that many designs were rushed, with little time to optimize or tune every instruction, but only those used most often. One infamous example was the VAX's INDEX instruction, which ran slower than an equivalent implementation using simpler operations.

For any given level of general performance, a RISC chip will typically have far fewer transistors dedicated to the core logic which originally allowed designers to increase the size of the register set and increase internal parallelism. Other features, which are typically found in RISC architectures are: 1 . Uniform instruction format, using a single word with the opcode in the same bit positions in every instruction, demanding less decoding; 2 . Identical general purpose registers, allowing any register to be used in any context, simplifying compiler design (although normally there are separate floating point registers); 3 . Simple addressing modes. Complex addressing performed via sequences of arithmetic and/or load-store operations; 4 . Few data types in hardware, some CISCs have byte string instructions, or support complex numbers; this is so far unlikely to be found on a RISC.